Traditionally, data access related to a memory device (e.g., a flash memory device, among others) is often implemented by employing tree-type decoders to efficiently use chip area. To mitigate memory component malfunctions (e.g., data access errors, among others) due to parasitic electronic effects (e.g., charge sharing, among others), conventional memory devices (e.g., flash memory devices, among others) require very accurate timing control signals to precharge the data access lines (e.g., bitlines, nodes in tree-type decoders, I/O lines, . . . ) before executing memory operations (e.g., read, write, refresh, erase, . . . ) by precisely estimating the parasitic electronic effects of related components (e.g., bitlines, wordlines, decoders, I/O lines, . . . ) within the memory device. It has been common practice to employ multiple precharge condition control signals and precharge condition charge outputs to account for the parasitic electronic effects (e.g., potential charge sharing, resistance, . . . ) among data access lines (e.g., bitlines, nodes in tree-type decoders, I/O lines, . . . ). This has conventionally increased the complexity of the timing scheme for the multiple precharge condition control signals and precharge condition charge outputs and can be related to increases in the malfunction of memory devices (e.g., data access errors, among others) resulting from failures to effectively manage the complex timing scheme employed in correspondingly complex memory device designs.
Computer memory systems have grown in complexity as higher volumes of memory have become available in ever decreasing package sizes. As the memory density has increased, power consumption and heat dissipation have become increasingly problematic parameters. Further, computing systems continue to be driven by a desire for faster processing, resulting in ever decreasing temporal windows for data access and compression of the signaling scheme used for data input and output (I/O) and thus, precisely choreographed signaling with very low error tolerances has become increasingly desirable.
Generally, information can be stored and maintained in one or more of a number of types of storage devices, such as memory devices. Memory devices can be subdivided into volatile and non-volatile types. Volatile memory devices generally lose their information if they lose power and typically require periodic refresh cycles to maintain their information. Volatile memory devices include, for example, random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), and the like. Non-volatile memory devices can maintain their information whether or not power is maintained to the memory devices. Non-volatile memory devices include, but are not limited to, flash memory, read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), non-volatile RAM, and the like.
The use of portable computer and electronic devices has greatly increased demand for high memory capacity, efficient, and reliable memory devices. Digital cameras, digital audio players, personal digital assistants, and the like, generally seek to employ large capacity memory devices (e.g., flash memory, smart media, or compact flash, among others). The increased demand for information storage can be commensurate with memory devices having an ever-increasing storage capacity (e.g., increase storage per die or chip). For example, a postage-stamp-sized piece of silicon can contain tens of millions of transistors, with each transistor as small as a few hundred nanometers.
The memory cells of a memory device (e.g., a nonvolatile memory core, a volatile memory core, a nonvolatile buffer, or a volatile buffer, among others) can typically be arranged in an array. A memory cell (e.g., a core cell or a buffer cell, among others) can be placed at each intersecting row and column in an array. Typically, a particular memory cell can be accessed by activating its row and then writing the state of its column or reading the state of the particular memory cell. Memory sizes can be defined by the row and column architecture. For example, a 1024 row by 1024 column memory array can define a memory device having one megabit of memory cells. The array rows can be referred to as wordlines and the array columns can be referred to as bitlines.
In memory cells, one or more bits of data can be stored in (e.g., a write) and read (e.g., a read) from respective memory cells. The memory operations (e.g., core operations or buffer operations, among others) to access memory cells and data associated therewith can be commonly performed by application of appropriate voltages to certain terminals of the memory cells. In a read or write operation the voltages can be applied so as to cause a charge to be removed, stored, or sensed in/from a charge storage layer of the memory cell.
The trend in semiconductor memory devices has been toward higher circuit density with higher numbers of bit cells per device, lower operating voltages, and higher access speeds. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels). However, as the desired scaling down of device dimensions occur, certain undesirable electronic effects can be increasingly problematic. It is desirable to scale down the size of memory devices while reducing or minimizing these undesirable electronic effects and maintaining and/or improving the functionality of such memory devices.
Errors in signal timing can propagate as a failure to properly manage multiple timing signals related to a memory device. These timing errors can produce logic failures and result in errors in the access of data on a memory device. Conventional memory devices are becoming increasingly complex in relation to signal timing as additional timing considerations are made to accommodate larger memory capacities, more dense memory device designs, and to overcome increasingly problematic parasitic electronic effects associated with scaling to more compact and dense memory devices.
Moreover, even where management of multiple signals is properly conducted, errors in data access can propagate as a result of engineering design errors and failures to account for the physical properties of a memory device (e.g., memory devices can have parasitic electronic effects such as, for example, capacitance, resistance, inductance, excessive time constants due to size, metal trace placement, orientation, and/or materials selections for device fabrication, among others, that can negatively impact proper data access in a memory device). Conventionally, addressing high density memory devices involves utilizing many data access lines (e.g., bitlines) and many access enable lines (e.g., wordlines) in close proximity. Many of these data access lines and access enable lines can have parasitic components to neighboring conductors (e.g., power rails, switched signal lines, other data access lines, . . . ) due to their proximity, often resulting in negative effects on data access, for example, cross talk or undefined signal levels, among others, and can result in reading/writing/refreshing/erasing data improperly. For example, it is inherently complex to determine small differential changes in signal levels on data access lines (e.g., bitlines) when measuring from an undefined state that can vary widely across a memory device. As memory systems become increasingly small and increasingly dense on the shrinking semiconductor real estate, parasitic electrical effects similarly can become increasingly problematic and can often result in lower quality memory or lower yield of satisfactory memories from a production process.
Methods and systems to reduce error propagation due to parasitic effects can add significant value to a memory system. Further, methods and systems to reduce timing signal complexity and ruggedness against parasitic electronic effects can also add significant value to a memory system.
A second issue in modern high density memory devices is power consumption. High power consumptions, even where temperature parameters are forgiving, are becoming increasingly less desirable as computing devices increasingly become independent of steady and enduring power supplies (e.g., battery powered devices such as laptop computers, cellular telephones, and personal digital assistants can be highly power conscious; future computing systems depending on “transmitted power” schema can likely be highly power conscious). Further, conventional memory devices, even where higher power consumption could be tolerated where wall or mains power sources were available to provide a surplus of power can be more environmentally friendly.
Additionally, where power density is high, thermal considerations are of serious concern in the industry. For example, the temperature in the core of a modern computer processor, if not properly managed, can easily destroy or severely damage the processor. Therefore, lower power consumption to reduce thermal issues is becoming more of a concern for high density memory products. Further, wicking thermal load can be insufficient to maintain favorable operating conditions at high performance levels in dense electrical systems. Other thermal management techniques can be of limited use or cost prohibitive. Reducing thermal loading by reducing power consumption can provide an avenue to optimize existing computer memories at comparatively low expense.
It is desirable to create simplified and robust systems and methods for temporal signaling within computer memory products to decrease error propagation and to simplify signal management. Further, it is desirable to efficiently manage power consumption to reduce overall power consumption and thermal loading in computer memory products.